// ******************************************************************************
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  pcie_harden_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2021/06/28
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2021/06/28 19:30:26 Create file
// ******************************************************************************

#ifndef PCIE_HARDEN_C_UNION_DEFINE_H
#define PCIE_HARDEN_C_UNION_DEFINE_H

/* Define the union csr_rst_cfg_pcie_harden_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sc_icg_en_pcie50_clk_apb_pcie_harden : 1;    /* [0] */
        u32 sc_icg_en_pcie50_clk_ap_axi_pcie_harden : 1; /* [1] */
        u32 icg_en_apb_pcie_harden : 5;                  /* [6:2] */
        u32 icg_en_mclk_pcie_harden : 4;                 /* [10:7] */
        u32 icg_en_rxoclk_pcie_harden : 16;              /* [26:11] */
        u32 rsv_0 : 5;                                   /* [31:27] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_pcie_harden_0_u;

/* Define the union csr_rst_cfg_pcie_harden_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_sds0_pma_tx_pcie_harden : 1; /* [0] */
        u32 icg_en_sds1_pma_tx_pcie_harden : 1; /* [1] */
        u32 icg_en_sds2_pma_tx_pcie_harden : 1; /* [2] */
        u32 icg_en_sds3_pma_tx_pcie_harden : 1; /* [3] */
        u32 icg_en_sds0_pma_rx_pcie_harden : 4; /* [7:4] */
        u32 icg_en_sds1_pma_rx_pcie_harden : 4; /* [11:8] */
        u32 icg_en_sds2_pma_rx_pcie_harden : 4; /* [15:12] */
        u32 icg_en_sds3_pma_rx_pcie_harden : 4; /* [19:16] */
        u32 rsv_1 : 12;                         /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_pcie_harden_1_u;

/* Define the union csr_rst_cfg_pcie_harden_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_apb_pcie_harden : 5;         /* [4:0] */
        u32 srst_req_sds0_pma_tx_pcie_harden : 1; /* [5] */
        u32 srst_req_sds1_pma_tx_pcie_harden : 1; /* [6] */
        u32 srst_req_sds2_pma_tx_pcie_harden : 1; /* [7] */
        u32 srst_req_sds3_pma_tx_pcie_harden : 1; /* [8] */
        u32 srst_req_sds0_pma_rx_pcie_harden : 4; /* [12:9] */
        u32 srst_req_sds1_pma_rx_pcie_harden : 4; /* [16:13] */
        u32 srst_req_sds2_pma_rx_pcie_harden : 4; /* [20:17] */
        u32 srst_req_sds3_pma_rx_pcie_harden : 4; /* [24:21] */
        u32 rsv_2 : 7;                            /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_pcie_harden_2_u;

/* Define the union csr_rst_cfg_pcie_harden_3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcie_ep_sys_clk_sel_pcie_harden : 1; /* [0] */
        u32 func_mbist_clk_sel_pcie_harden : 1;  /* [1] */
        u32 icg_en_probe : 1;                    /* [2] */
        u32 sds_mclk_icg_en_sel : 4;             /* [6:3] */
        u32 pcie_perstn_enable : 4;              /* [10:7] */
        u32 pcie_perstn_clear : 4;               /* [14:11] */
        u32 probe_mode : 1;                      /* [15] */
        u32 probe_sds_ep_sel : 1;                /* [16] */
        u32 sds_mclk_ckd_icg_en_sel : 4;         /* [20:17] */
        u32 mclk_ckd_div_cfg : 4;                /* [24:21] */
        u32 icg_en_mclk_ckd : 4;                 /* [28:25] */
        u32 rsv_3 : 3;                           /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_pcie_harden_3_u;

/* Define the union csr_clkreq_h_filter_pcie_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 bord2pm_refclk_req_filter_hwid : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_clkreq_h_filter_pcie_harden_u;

/* Define the union csr_clkreq_l_filter_pcie_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 bord2pm_refclk_req_filter_lwid : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_clkreq_l_filter_pcie_harden_u;

/* Define the union csr_rst_cfg_sml2_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_sml_sml2_harden : 1;        /* [0] */
        u32 icg_en_sml_div2_sml2_harden : 1;   /* [1] */
        u32 icg_en_smeg_sml2_harden : 1;       /* [2] */
        u32 icg_en_ring_sml2_harden : 1;       /* [3] */
        u32 srst_req_sml_sml2_harden : 1;      /* [4] */
        u32 srst_req_sml_div2_sml2_harden : 1; /* [5] */
        u32 srst_req_smeg_sml2_harden : 1;     /* [6] */
        u32 srst_req_ring_sml2_harden : 1;     /* [7] */
        u32 rsv_4 : 24;                        /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_sml2_harden_u;

/* Define the union csr_rst_cfg_sml3_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_sml_sml3_harden : 1;        /* [0] */
        u32 icg_en_sml_div2_sml3_harden : 1;   /* [1] */
        u32 icg_en_smeg_sml3_harden : 1;       /* [2] */
        u32 icg_en_ring_sml3_harden : 1;       /* [3] */
        u32 srst_req_sml_sml3_harden : 1;      /* [4] */
        u32 srst_req_sml_div2_sml3_harden : 1; /* [5] */
        u32 srst_req_smeg_sml3_harden : 1;     /* [6] */
        u32 srst_req_ring_sml3_harden : 1;     /* [7] */
        u32 rsv_5 : 24;                        /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_sml3_harden_u;

/* Define the union csr_sml2_power_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml_iso_en_sml2_harden : 1;        /* [0] */
        u32 sml_mtcmos_pwr_on_sml2_harden : 1; /* [1] */
        u32 srst_req_wol_por_sml2_harden : 1;  /* [2] */
        u32 srst_req_wol_comb_sml2_harden : 1; /* [3] */
        u32 wol_rst_sel_sml2_harden : 1;       /* [4] */
        u32 rsv_6 : 27;                        /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sml2_power_cfg_u;

/* Define the union csr_sml2_power_ack_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml_mtcmos_pwr_ack_sml2_harden : 1; /* [0] */
        u32 rsv_7 : 31;                         /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sml2_power_ack_u;

/* Define the union csr_sml3_power_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml_iso_en_sml3_harden : 1;        /* [0] */
        u32 sml_mtcmos_pwr_on_sml3_harden : 1; /* [1] */
        u32 srst_req_wol_por_sml3_harden : 1;  /* [2] */
        u32 srst_req_wol_comb_sml3_harden : 1; /* [3] */
        u32 wol_rst_sel_sml3_harden : 1;       /* [4] */
        u32 rsv_8 : 27;                        /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sml3_power_cfg_u;

/* Define the union csr_sml3_power_ack_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml_mtcmos_pwr_ack_sml3_harden : 1; /* [0] */
        u32 rsv_9 : 31;                         /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sml3_power_ack_u;

/* Define the union csr_rst_cfg_cpi_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_cpi_octl_harden : 1;            /* [0] */
        u32 icg_en_cpi_dma_harden : 1;             /* [1] */
        u32 icg_en_ring_cpi_ctrl_harden : 1;       /* [2] */
        u32 icg_en_hva_cpi_ctrl_harden : 1;        /* [3] */
        u32 icg_en_cpi_div2_cpi_ctrl_harden : 1;   /* [4] */
        u32 icg_en_hva_apb_cpi_ctrl_harden : 1;    /* [5] */
        u32 icg_en_axi_cpi_ctrl_harden : 1;        /* [6] */
        u32 icg_en_1588_cpi_ctrl_harden : 1;       /* [7] */
        u32 icg_en_cpi_ctrl_harden : 1;            /* [8] */
        u32 srst_req_cpi_octl_harden : 1;          /* [9] */
        u32 srst_req_cpi_dma_harden : 1;           /* [10] */
        u32 srst_req_ring_cpi_ctrl_harden : 1;     /* [11] */
        u32 srst_req_hva_cpi_ctrl_harden : 1;      /* [12] */
        u32 srst_req_cpi_div2_cpi_ctrl_harden : 1; /* [13] */
        u32 srst_req_hva_apb_cpi_ctrl_harden : 1;  /* [14] */
        u32 srst_req_axi_cpi_ctrl_harden : 1;      /* [15] */
        u32 srst_req_1588_cpi_ctrl_harden : 1;     /* [16] */
        u32 srst_req_cpi_ctrl_harden : 1;          /* [17] */
        u32 icg_en_cpi_500m : 1;                   /* [18] */
        u32 srst_req_cpi_500m : 1;                 /* [19] */
        u32 rsv_10 : 12;                           /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_cpi_harden_u;

/* Define the union csr_rst_cfg_ipsutx_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_ipsutx_ipsutx_harden : 1;   /* [0] */
        u32 icg_en_ring_ipsutx_harden : 1;     /* [1] */
        u32 srst_req_ipsutx_ipsutx_harden : 1; /* [2] */
        u32 srst_req_ring_ipsutx_harden : 1;   /* [3] */
        u32 rsv_11 : 28;                       /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_ipsutx_harden_u;

/* Define the union csr_rst_cfg_perx_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_perx_perx_harden : 1;   /* [0] */
        u32 srst_req_perx_perx_harden : 1; /* [1] */
        u32 rsv_12 : 30;                   /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_perx_harden_u;

/* Define the union csr_ring_sta_ipsutx_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ipsutx_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */
        u32 rsv_13 : 22;                          /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_ipsutx_harden_u;

/* Define the union csr_ring_sta_sml2_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml2_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */
        u32 rsv_14 : 22;                        /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_sml2_harden_u;

/* Define the union csr_ring_sta_sml3_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml3_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */
        u32 rsv_15 : 22;                        /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_sml3_harden_u;

/* Define the union csr_ring_sta_cpi_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cpi_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */
        u32 rsv_16 : 22;                       /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_cpi_harden_u;

/* Define the union csr_pll1_cfg_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_cfg0 : 16; /* [15:0] */
        u32 pll1_cfg1 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_cfg_0_u;

/* Define the union csr_pll1_cfg_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_cfg2 : 16; /* [15:0] */
        u32 pll1_cfg3 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_cfg_1_u;

/* Define the union csr_pll1_cfg_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_cfg4 : 16; /* [15:0] */
        u32 pll1_cfg5 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_cfg_2_u;

/* Define the union csr_pll1_cfg_3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_cfg6 : 16; /* [15:0] */
        u32 pll1_cfg7 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_cfg_3_u;

/* Define the union csr_pll1_cfg_4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_cfg8 : 16; /* [15:0] */
        u32 pll1_cfg9 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_cfg_4_u;

/* Define the union csr_pll1_cfg_5_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_cfg10 : 16; /* [15:0] */
        u32 rsv_17 : 16;     /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_cfg_5_u;

/* Define the union csr_pll1_cfg_6_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_pllfctrl0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_cfg_6_u;

/* Define the union csr_pll1_cfg_7_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_pllfctrl1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_cfg_7_u;

/* Define the union csr_pll1_cfg_8_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_bypass_external_n : 1; /* [0] */
        u32 pll1_peri_mode : 1;         /* [1] */
        u32 dll_en_pll1 : 1;            /* [2] */
        u32 probe_mode_pll1 : 1;        /* [3] */
        u32 icg_en_probe_pll1 : 1;      /* [4] */
        u32 rsv_18 : 27;                /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_cfg_8_u;

/* Define the union csr_pll1_state_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_state0 : 16; /* [15:0] */
        u32 pll1_state1 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_state_0_u;

/* Define the union csr_pll1_state_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll1_lock : 1; /* [0] */
        u32 rsv_19 : 31;   /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll1_state_1_u;

/* Define the union csr_tsensor_cfg_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sc_temp_ctl : 14; /* [13:0] */
        u32 rsv_20 : 18;      /* [31:14] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_tsensor_cfg_0_u;

/* Define the union csr_tsensor_cfg_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tsensor_temp_low_lvl : 10;  /* [9:0] */
        u32 tsensor_temp_high_lvl : 10; /* [19:10] */
        u32 tsensor_int_en : 2;         /* [21:20] */
        u32 rsv_21 : 10;                /* [31:22] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_tsensor_cfg_1_u;

/* Define the union csr_tsensor_satus_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 temp_val : 10;    /* [9:0] */
        u32 temp_val_vld : 1; /* [10] */
        u32 rsv_22 : 21;      /* [31:11] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_tsensor_satus_0_u;

/* Define the union csr_rst_cfg_pcie_harden_4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sc_icg_en_pcie50_clk_apb : 2;               /* [1:0] */
        u32 sc_icg_en_pcie50_clk_ap_axi : 5;            /* [6:2] */
        u32 sc_icg_en_pcie50_clk_tl_axi : 1;            /* [7] */
        u32 sc_icg_en_pcie50_clk_core_tl_port : 4;      /* [11:8] */
        u32 sc_icg_en_pcie50_clk_core_tl_port_div : 4;  /* [15:12] */
        u32 sc_icg_en_pcie50_clk_core_tl_common : 1;    /* [16] */
        u32 sc_icg_en_pcie50_clk_core_phy_port : 4;     /* [20:17] */
        u32 sc_icg_en_pcie50_clk_core_phy_port_div : 4; /* [24:21] */
        u32 sc_icg_en_pcie50_clk_core_phy_common : 1;   /* [25] */
        u32 sc_icg_en_pcie50_clk_pcs_logic_common : 1;  /* [26] */
        u32 sc_icg_en_pcie50_clk_pcs_apb : 1;           /* [27] */
        u32 rsv_23 : 4;                                 /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_pcie_harden_4_u;

/* Define the union csr_rst_cfg_pcie_harden_5_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sc_icg_en_pcie50_clk_core_phy_lane : 16; /* [15:0] */
        u32 sc_icg_en_pcie50_clk_pipe_lane : 16;     /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_pcie_harden_5_u;

/* Define the union csr_rst_cfg_pcie_harden_6_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sc_icg_en_pcie50_clk_pcs_logic : 16;     /* [15:0] */
        u32 sc_icg_en_pcie50_clk_pcs_logic_div : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_pcie_harden_6_u;

/* Define the union csr_rst_cfg_pcie_harden_7_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sc_icg_en_pcie50_clk_pcs_tx : 16; /* [15:0] */
        u32 sc_icg_en_pcie50_clk_pcs_rx : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_pcie_harden_7_u;


// ==============================================================================
/* Define the global struct */
typedef struct {
    volatile csr_rst_cfg_pcie_harden_0_u rst_cfg_pcie_harden_0;             /* 0 */
    volatile csr_rst_cfg_pcie_harden_1_u rst_cfg_pcie_harden_1;             /* 4 */
    volatile csr_rst_cfg_pcie_harden_2_u rst_cfg_pcie_harden_2;             /* 8 */
    volatile csr_rst_cfg_pcie_harden_3_u rst_cfg_pcie_harden_3;             /* C */
    volatile csr_clkreq_h_filter_pcie_harden_u clkreq_h_filter_pcie_harden; /* 10 */
    volatile csr_clkreq_l_filter_pcie_harden_u clkreq_l_filter_pcie_harden; /* 14 */
    volatile csr_rst_cfg_sml2_harden_u rst_cfg_sml2_harden;                 /* 18 */
    volatile csr_rst_cfg_sml3_harden_u rst_cfg_sml3_harden;                 /* 1C */
    volatile csr_sml2_power_cfg_u sml2_power_cfg;                           /* 20 */
    volatile csr_sml2_power_ack_u sml2_power_ack;                           /* 24 */
    volatile csr_sml3_power_cfg_u sml3_power_cfg;                           /* 28 */
    volatile csr_sml3_power_ack_u sml3_power_ack;                           /* 2C */
    volatile csr_rst_cfg_cpi_harden_u rst_cfg_cpi_harden;                   /* 30 */
    volatile csr_rst_cfg_ipsutx_harden_u rst_cfg_ipsutx_harden;             /* 34 */
    volatile csr_rst_cfg_perx_harden_u rst_cfg_perx_harden;                 /* 38 */
    volatile csr_ring_sta_ipsutx_harden_u ring_sta_ipsutx_harden;           /* 3C */
    volatile csr_ring_sta_sml2_harden_u ring_sta_sml2_harden;               /* 40 */
    volatile csr_ring_sta_sml3_harden_u ring_sta_sml3_harden;               /* 44 */
    volatile csr_ring_sta_cpi_harden_u ring_sta_cpi_harden;                 /* 48 */
    volatile csr_pll1_cfg_0_u pll1_cfg_0;                                   /* 4C */
    volatile csr_pll1_cfg_1_u pll1_cfg_1;                                   /* 50 */
    volatile csr_pll1_cfg_2_u pll1_cfg_2;                                   /* 54 */
    volatile csr_pll1_cfg_3_u pll1_cfg_3;                                   /* 58 */
    volatile csr_pll1_cfg_4_u pll1_cfg_4;                                   /* 5C */
    volatile csr_pll1_cfg_5_u pll1_cfg_5;                                   /* 60 */
    volatile csr_pll1_cfg_6_u pll1_cfg_6;                                   /* 64 */
    volatile csr_pll1_cfg_7_u pll1_cfg_7;                                   /* 68 */
    volatile csr_pll1_cfg_8_u pll1_cfg_8;                                   /* 6C */
    volatile csr_pll1_state_0_u pll1_state_0;                               /* 70 */
    volatile csr_pll1_state_1_u pll1_state_1;                               /* 74 */
    volatile csr_tsensor_cfg_0_u tsensor_cfg_0;                             /* 78 */
    volatile csr_tsensor_cfg_1_u tsensor_cfg_1;                             /* 7C */
    volatile csr_tsensor_satus_0_u tsensor_satus_0;                         /* 80 */
    volatile csr_rst_cfg_pcie_harden_4_u rst_cfg_pcie_harden_4;             /* 84 */
    volatile csr_rst_cfg_pcie_harden_5_u rst_cfg_pcie_harden_5;             /* 88 */
    volatile csr_rst_cfg_pcie_harden_6_u rst_cfg_pcie_harden_6;             /* 8C */
    volatile csr_rst_cfg_pcie_harden_7_u rst_cfg_pcie_harden_7;             /* 90 */
} S_pcie_harden_REGS_TYPE;

/* Declare the struct pointor of the module pcie_harden */
extern volatile S_pcie_harden_REGS_TYPE *goppcie_hardenAllReg;

/* Declare the functions that set the member value */
int iSetRST_CFG_PCIE_HARDEN_0_sc_icg_en_pcie50_clk_apb_pcie_harden(unsigned int usc_icg_en_pcie50_clk_apb_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_0_sc_icg_en_pcie50_clk_ap_axi_pcie_harden(
    unsigned int usc_icg_en_pcie50_clk_ap_axi_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_0_icg_en_apb_pcie_harden(unsigned int uicg_en_apb_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_0_icg_en_mclk_pcie_harden(unsigned int uicg_en_mclk_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_0_icg_en_rxoclk_pcie_harden(unsigned int uicg_en_rxoclk_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds0_pma_tx_pcie_harden(unsigned int uicg_en_sds0_pma_tx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds1_pma_tx_pcie_harden(unsigned int uicg_en_sds1_pma_tx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds2_pma_tx_pcie_harden(unsigned int uicg_en_sds2_pma_tx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds3_pma_tx_pcie_harden(unsigned int uicg_en_sds3_pma_tx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds0_pma_rx_pcie_harden(unsigned int uicg_en_sds0_pma_rx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds1_pma_rx_pcie_harden(unsigned int uicg_en_sds1_pma_rx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds2_pma_rx_pcie_harden(unsigned int uicg_en_sds2_pma_rx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds3_pma_rx_pcie_harden(unsigned int uicg_en_sds3_pma_rx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_2_srst_req_apb_pcie_harden(unsigned int usrst_req_apb_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds0_pma_tx_pcie_harden(unsigned int usrst_req_sds0_pma_tx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds1_pma_tx_pcie_harden(unsigned int usrst_req_sds1_pma_tx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds2_pma_tx_pcie_harden(unsigned int usrst_req_sds2_pma_tx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds3_pma_tx_pcie_harden(unsigned int usrst_req_sds3_pma_tx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds0_pma_rx_pcie_harden(unsigned int usrst_req_sds0_pma_rx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds1_pma_rx_pcie_harden(unsigned int usrst_req_sds1_pma_rx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds2_pma_rx_pcie_harden(unsigned int usrst_req_sds2_pma_rx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds3_pma_rx_pcie_harden(unsigned int usrst_req_sds3_pma_rx_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_3_pcie_ep_sys_clk_sel_pcie_harden(unsigned int upcie_ep_sys_clk_sel_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_3_func_mbist_clk_sel_pcie_harden(unsigned int ufunc_mbist_clk_sel_pcie_harden);
int iSetRST_CFG_PCIE_HARDEN_3_icg_en_probe(unsigned int uicg_en_probe);
int iSetRST_CFG_PCIE_HARDEN_3_sds_mclk_icg_en_sel(unsigned int usds_mclk_icg_en_sel);
int iSetRST_CFG_PCIE_HARDEN_3_pcie_perstn_enable(unsigned int upcie_perstn_enable);
int iSetRST_CFG_PCIE_HARDEN_3_pcie_perstn_clear(unsigned int upcie_perstn_clear);
int iSetRST_CFG_PCIE_HARDEN_3_probe_mode(unsigned int uprobe_mode);
int iSetRST_CFG_PCIE_HARDEN_3_probe_sds_ep_sel(unsigned int uprobe_sds_ep_sel);
int iSetRST_CFG_PCIE_HARDEN_3_sds_mclk_ckd_icg_en_sel(unsigned int usds_mclk_ckd_icg_en_sel);
int iSetRST_CFG_PCIE_HARDEN_3_mclk_ckd_div_cfg(unsigned int umclk_ckd_div_cfg);
int iSetRST_CFG_PCIE_HARDEN_3_icg_en_mclk_ckd(unsigned int uicg_en_mclk_ckd);
int iSetCLKREQ_H_FILTER_PCIE_HARDEN_bord2pm_refclk_req_filter_hwid(unsigned int ubord2pm_refclk_req_filter_hwid);
int iSetCLKREQ_L_FILTER_PCIE_HARDEN_bord2pm_refclk_req_filter_lwid(unsigned int ubord2pm_refclk_req_filter_lwid);
int iSetRST_CFG_SML2_HARDEN_icg_en_sml_sml2_harden(unsigned int uicg_en_sml_sml2_harden);
int iSetRST_CFG_SML2_HARDEN_icg_en_sml_div2_sml2_harden(unsigned int uicg_en_sml_div2_sml2_harden);
int iSetRST_CFG_SML2_HARDEN_icg_en_smeg_sml2_harden(unsigned int uicg_en_smeg_sml2_harden);
int iSetRST_CFG_SML2_HARDEN_icg_en_ring_sml2_harden(unsigned int uicg_en_ring_sml2_harden);
int iSetRST_CFG_SML2_HARDEN_srst_req_sml_sml2_harden(unsigned int usrst_req_sml_sml2_harden);
int iSetRST_CFG_SML2_HARDEN_srst_req_sml_div2_sml2_harden(unsigned int usrst_req_sml_div2_sml2_harden);
int iSetRST_CFG_SML2_HARDEN_srst_req_smeg_sml2_harden(unsigned int usrst_req_smeg_sml2_harden);
int iSetRST_CFG_SML2_HARDEN_srst_req_ring_sml2_harden(unsigned int usrst_req_ring_sml2_harden);
int iSetRST_CFG_SML3_HARDEN_icg_en_sml_sml3_harden(unsigned int uicg_en_sml_sml3_harden);
int iSetRST_CFG_SML3_HARDEN_icg_en_sml_div2_sml3_harden(unsigned int uicg_en_sml_div2_sml3_harden);
int iSetRST_CFG_SML3_HARDEN_icg_en_smeg_sml3_harden(unsigned int uicg_en_smeg_sml3_harden);
int iSetRST_CFG_SML3_HARDEN_icg_en_ring_sml3_harden(unsigned int uicg_en_ring_sml3_harden);
int iSetRST_CFG_SML3_HARDEN_srst_req_sml_sml3_harden(unsigned int usrst_req_sml_sml3_harden);
int iSetRST_CFG_SML3_HARDEN_srst_req_sml_div2_sml3_harden(unsigned int usrst_req_sml_div2_sml3_harden);
int iSetRST_CFG_SML3_HARDEN_srst_req_smeg_sml3_harden(unsigned int usrst_req_smeg_sml3_harden);
int iSetRST_CFG_SML3_HARDEN_srst_req_ring_sml3_harden(unsigned int usrst_req_ring_sml3_harden);
int iSetSML2_POWER_CFG_sml_iso_en_sml2_harden(unsigned int usml_iso_en_sml2_harden);
int iSetSML2_POWER_CFG_sml_mtcmos_pwr_on_sml2_harden(unsigned int usml_mtcmos_pwr_on_sml2_harden);
int iSetSML2_POWER_CFG_srst_req_wol_por_sml2_harden(unsigned int usrst_req_wol_por_sml2_harden);
int iSetSML2_POWER_CFG_srst_req_wol_comb_sml2_harden(unsigned int usrst_req_wol_comb_sml2_harden);
int iSetSML2_POWER_CFG_wol_rst_sel_sml2_harden(unsigned int uwol_rst_sel_sml2_harden);
int iSetSML2_POWER_ACK_sml_mtcmos_pwr_ack_sml2_harden(unsigned int usml_mtcmos_pwr_ack_sml2_harden);
int iSetSML3_POWER_CFG_sml_iso_en_sml3_harden(unsigned int usml_iso_en_sml3_harden);
int iSetSML3_POWER_CFG_sml_mtcmos_pwr_on_sml3_harden(unsigned int usml_mtcmos_pwr_on_sml3_harden);
int iSetSML3_POWER_CFG_srst_req_wol_por_sml3_harden(unsigned int usrst_req_wol_por_sml3_harden);
int iSetSML3_POWER_CFG_srst_req_wol_comb_sml3_harden(unsigned int usrst_req_wol_comb_sml3_harden);
int iSetSML3_POWER_CFG_wol_rst_sel_sml3_harden(unsigned int uwol_rst_sel_sml3_harden);
int iSetSML3_POWER_ACK_sml_mtcmos_pwr_ack_sml3_harden(unsigned int usml_mtcmos_pwr_ack_sml3_harden);
int iSetRST_CFG_CPI_HARDEN_icg_en_cpi_octl_harden(unsigned int uicg_en_cpi_octl_harden);
int iSetRST_CFG_CPI_HARDEN_icg_en_cpi_dma_harden(unsigned int uicg_en_cpi_dma_harden);
int iSetRST_CFG_CPI_HARDEN_icg_en_ring_cpi_ctrl_harden(unsigned int uicg_en_ring_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_icg_en_hva_cpi_ctrl_harden(unsigned int uicg_en_hva_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_icg_en_cpi_div2_cpi_ctrl_harden(unsigned int uicg_en_cpi_div2_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_icg_en_hva_apb_cpi_ctrl_harden(unsigned int uicg_en_hva_apb_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_icg_en_axi_cpi_ctrl_harden(unsigned int uicg_en_axi_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_icg_en_1588_cpi_ctrl_harden(unsigned int uicg_en_1588_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_icg_en_cpi_ctrl_harden(unsigned int uicg_en_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_srst_req_cpi_octl_harden(unsigned int usrst_req_cpi_octl_harden);
int iSetRST_CFG_CPI_HARDEN_srst_req_cpi_dma_harden(unsigned int usrst_req_cpi_dma_harden);
int iSetRST_CFG_CPI_HARDEN_srst_req_ring_cpi_ctrl_harden(unsigned int usrst_req_ring_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_srst_req_hva_cpi_ctrl_harden(unsigned int usrst_req_hva_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_srst_req_cpi_div2_cpi_ctrl_harden(unsigned int usrst_req_cpi_div2_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_srst_req_hva_apb_cpi_ctrl_harden(unsigned int usrst_req_hva_apb_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_srst_req_axi_cpi_ctrl_harden(unsigned int usrst_req_axi_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_srst_req_1588_cpi_ctrl_harden(unsigned int usrst_req_1588_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_srst_req_cpi_ctrl_harden(unsigned int usrst_req_cpi_ctrl_harden);
int iSetRST_CFG_CPI_HARDEN_icg_en_cpi_500m(unsigned int uicg_en_cpi_500m);
int iSetRST_CFG_CPI_HARDEN_srst_req_cpi_500m(unsigned int usrst_req_cpi_500m);
int iSetRST_CFG_IPSUTX_HARDEN_icg_en_ipsutx_ipsutx_harden(unsigned int uicg_en_ipsutx_ipsutx_harden);
int iSetRST_CFG_IPSUTX_HARDEN_icg_en_ring_ipsutx_harden(unsigned int uicg_en_ring_ipsutx_harden);
int iSetRST_CFG_IPSUTX_HARDEN_srst_req_ipsutx_ipsutx_harden(unsigned int usrst_req_ipsutx_ipsutx_harden);
int iSetRST_CFG_IPSUTX_HARDEN_srst_req_ring_ipsutx_harden(unsigned int usrst_req_ring_ipsutx_harden);
int iSetRST_CFG_PERX_HARDEN_icg_en_perx_perx_harden(unsigned int uicg_en_perx_perx_harden);
int iSetRST_CFG_PERX_HARDEN_srst_req_perx_perx_harden(unsigned int usrst_req_perx_perx_harden);
int iSetRING_STA_IPSUTX_HARDEN_ipsutx_harden_rs_nd_pe_crdt_sta(unsigned int uipsutx_harden_rs_nd_pe_crdt_sta);
int iSetRING_STA_SML2_HARDEN_sml2_harden_rs_nd_pe_crdt_sta(unsigned int usml2_harden_rs_nd_pe_crdt_sta);
int iSetRING_STA_SML3_HARDEN_sml3_harden_rs_nd_pe_crdt_sta(unsigned int usml3_harden_rs_nd_pe_crdt_sta);
int iSetRING_STA_CPI_HARDEN_cpi_harden_rs_nd_pe_crdt_sta(unsigned int ucpi_harden_rs_nd_pe_crdt_sta);
int iSetPLL1_CFG_0_pll1_cfg0(unsigned int upll1_cfg0);
int iSetPLL1_CFG_0_pll1_cfg1(unsigned int upll1_cfg1);
int iSetPLL1_CFG_1_pll1_cfg2(unsigned int upll1_cfg2);
int iSetPLL1_CFG_1_pll1_cfg3(unsigned int upll1_cfg3);
int iSetPLL1_CFG_2_pll1_cfg4(unsigned int upll1_cfg4);
int iSetPLL1_CFG_2_pll1_cfg5(unsigned int upll1_cfg5);
int iSetPLL1_CFG_3_pll1_cfg6(unsigned int upll1_cfg6);
int iSetPLL1_CFG_3_pll1_cfg7(unsigned int upll1_cfg7);
int iSetPLL1_CFG_4_pll1_cfg8(unsigned int upll1_cfg8);
int iSetPLL1_CFG_4_pll1_cfg9(unsigned int upll1_cfg9);
int iSetPLL1_CFG_5_pll1_cfg10(unsigned int upll1_cfg10);
int iSetPLL1_CFG_6_pll1_pllfctrl0(unsigned int upll1_pllfctrl0);
int iSetPLL1_CFG_7_pll1_pllfctrl1(unsigned int upll1_pllfctrl1);
int iSetPLL1_CFG_8_pll1_bypass_external_n(unsigned int upll1_bypass_external_n);
int iSetPLL1_CFG_8_pll1_peri_mode(unsigned int upll1_peri_mode);
int iSetPLL1_CFG_8_dll_en_pll1(unsigned int udll_en_pll1);
int iSetPLL1_CFG_8_probe_mode_pll1(unsigned int uprobe_mode_pll1);
int iSetPLL1_CFG_8_icg_en_probe_pll1(unsigned int uicg_en_probe_pll1);
int iSetPLL1_STATE_0_pll1_state0(unsigned int upll1_state0);
int iSetPLL1_STATE_0_pll1_state1(unsigned int upll1_state1);
int iSetPLL1_STATE_1_pll1_lock(unsigned int upll1_lock);
int iSetTSENSOR_CFG_0_sc_temp_ctl(unsigned int usc_temp_ctl);
int iSetTSENSOR_CFG_1_tsensor_temp_low_lvl(unsigned int utsensor_temp_low_lvl);
int iSetTSENSOR_CFG_1_tsensor_temp_high_lvl(unsigned int utsensor_temp_high_lvl);
int iSetTSENSOR_CFG_1_tsensor_int_en(unsigned int utsensor_int_en);
int iSetTSENSOR_SATUS_0_temp_val(unsigned int utemp_val);
int iSetTSENSOR_SATUS_0_temp_val_vld(unsigned int utemp_val_vld);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_apb(unsigned int usc_icg_en_pcie50_clk_apb);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_ap_axi(unsigned int usc_icg_en_pcie50_clk_ap_axi);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_tl_axi(unsigned int usc_icg_en_pcie50_clk_tl_axi);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_tl_port(unsigned int usc_icg_en_pcie50_clk_core_tl_port);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_tl_port_div(
    unsigned int usc_icg_en_pcie50_clk_core_tl_port_div);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_tl_common(unsigned int usc_icg_en_pcie50_clk_core_tl_common);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_phy_port(unsigned int usc_icg_en_pcie50_clk_core_phy_port);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_phy_port_div(
    unsigned int usc_icg_en_pcie50_clk_core_phy_port_div);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_phy_common(unsigned int usc_icg_en_pcie50_clk_core_phy_common);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_pcs_logic_common(
    unsigned int usc_icg_en_pcie50_clk_pcs_logic_common);
int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_pcs_apb(unsigned int usc_icg_en_pcie50_clk_pcs_apb);
int iSetRST_CFG_PCIE_HARDEN_5_sc_icg_en_pcie50_clk_core_phy_lane(unsigned int usc_icg_en_pcie50_clk_core_phy_lane);
int iSetRST_CFG_PCIE_HARDEN_5_sc_icg_en_pcie50_clk_pipe_lane(unsigned int usc_icg_en_pcie50_clk_pipe_lane);
int iSetRST_CFG_PCIE_HARDEN_6_sc_icg_en_pcie50_clk_pcs_logic(unsigned int usc_icg_en_pcie50_clk_pcs_logic);
int iSetRST_CFG_PCIE_HARDEN_6_sc_icg_en_pcie50_clk_pcs_logic_div(unsigned int usc_icg_en_pcie50_clk_pcs_logic_div);
int iSetRST_CFG_PCIE_HARDEN_7_sc_icg_en_pcie50_clk_pcs_tx(unsigned int usc_icg_en_pcie50_clk_pcs_tx);
int iSetRST_CFG_PCIE_HARDEN_7_sc_icg_en_pcie50_clk_pcs_rx(unsigned int usc_icg_en_pcie50_clk_pcs_rx);


#endif // PCIE_HARDEN_C_UNION_DEFINE_H
